Syllubus
Schedule
DEMO
FAQs
Trainer
Syllubus
- ACE versus CHI
- Cache, System memory, secondary memory
- Page tables – Virtual and Physical address
- Cache, Cache line, Cache coherence, Snoop, CCI
- Hardware and software managed coherency
- MOESI
- 7 States of Cache line
- Architecture Overview – RN, HN, SN
- Architecture Layers
- Topology
- Transaction Classification
- Component Naming
- Channels Overview
- Channel Mapping for Different Nodes
- Channel Fields – Opcodes
- Transaction Structure
- Transaction Identifier Fields
- Logical Processor Identifier
- Ordering
- Address, Control, and Data
- Data Transfer
- Request Retry
- Cache, System memory, secondary memory
- Page tables – Virtual and Physical address
- Flit
- Interface activation and deactivation
- Transaction flow for write, read, dataless, CMO, Non-CMO
- Combined write transactions, Atomic transactions
- Misc. transactions
- Transaction retry sequence
- Snoop transactions
- Response types
- Ordering
- Transaction attributes
- Forwarding snoop transactions
- Exclusive accesses
- Cache line states
- Request types
- Snoop request types
- Request types and corresponding Snoop requests
- Response types
- Silent cache state transitions
- Cache state transitions at a Requester
- Cache state transitions at a Snoopee
- Returning Data with Snoop response
- Do not transition to SD
- Hazard conditions
- Read transaction flows
- Dataless transaction flows
- Write transaction flows
- Atomic transaction flows
- Stash transaction flows
- Hazard handling examples
- Overview
- Exclusive monitors
- Exclusive transactions
- Write with Stash hint
- Independent Stash request
- Stash target identifiers
- Stash messages
- DVM transaction flow
- DVM Operation types
- DVM Operations
- Error types
- Error response fields
- Errors and transaction structure
- Error response use by transaction type
- Poison
- Data Check
Schedule
| Course | AMBA CHI training |
|---|---|
| Duration | Live training : 6 weeks |
| Next Batch | |
| Schedule | Saturday, Sunday, 10AM to 1:30PM |
| Tool | This is protocol only training, doesn’t require any tool access. |
| Mode of training | Live training for minimum of 10 participants or corporate training eLearning with dedicated mentor for doubt clarifications. |
| Assignments | 5 |
DEMO
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Exposure to standard bus protocols
- Exposure to Testbench component coding using SystemVerilog
Each session of course is recorded, missed session videos will be s
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Trainer
Experienced Trainer
- 12 years of work experience in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Play Video
- 1-1 Dedicated Mentor Support
- mock interview
- Support with resume update