synthesis-and-sta
1-1 training Highlights
- 150 hours of 1-1 training at student flexible timings
- Support with office work debug (for working professionals)
- Complete guided project support, and 24x7 tool access for hands on practice
- Course content can be customized(topics added and removed) as per student requirements
- Trainer support outside teaching hours.
- Regular mock interviews and assessment tests for performance tracking
Course content - Hourly breakup
| Topic | Duration(Hours) |
|---|---|
| Verilog constructs | 2 |
| Combinational logic implementation | 5 |
| Sequential logic implementation | 3 |
| Advanced Verilog language constructs | 10 |
| Verilog projects | |
| Memory verilog coding and TB development | 3 |
| Synchronous and Asynchronous FIFO design and verification | 4 |
| SPI Controller | 4 |
| Pattern detector | 2 |
| CRC generation | 2 |
| Total | 35 |
| Topic | Duration(Hours) |
|---|---|
| Data types, operators, arrays | 6 |
| Object oriented programming | 12 |
| Interface, program, Inter process synchronization | 3 |
| Constraints and randomization | 4 |
| Functional and code coverage | 4 |
| Assertions | 3 |
| Other SV language constructs | 3 |
| SV Test bench setup for memory | 5 |
| Total | 40 |
| Topic | Duration(Hours) |
|---|---|
| UVM base classes, UVM TB hierarchy | 4 |
| Root, objections, phases, Command line processor | 4 |
| Reporting classes | 3 |
| UVM config DB and Resource DB, Factory | 4 |
| TLM1.0 | 4 |
| Sequences, sequence library | 4 |
| RAL, register model coding | 3 |
| UVM Test bench setup for memory | 4 |
| Total | 30 |
| Topic | Duration(Hours) |
|---|---|
| SPI Protocol | 2 |
| I2C Protocol | 2 |
| APB protocol | 1 |
| AHB protocol | 5 |
| AXI protocol | 5 |
| Total | 15 |
| Topic | Duration(Hours) |
|---|---|
| AXI VIP development using SV & UVM | 6 |
| Ethernet MAC functional verification using SV & UVM | 24 |
| Total | 30 |